1. Field of the Invention
The present invention relates to a method and apparatus for aligning a clock signal and a data strobe signal in a system comprising a memory controller and a memory. More particularly, this invention relates to determining a delay applied to the data strobe signal to align it with the clock signal.
2. Description of the Prior Art
In a memory system comprising a memory controller and a memory, it is known for the memory controller to carry out a write levelling calibration of the memory system during an initiation phase in which the relative timing of a clock signal (CLK) and a data strobe signal (DQS) is adjusted. The clock signal is distributed by the memory controller to the memory modules of the memory system as a reference for all components of the system and the data strobe signal indicates the points at which a data signal (DQ) transmitted between the memory controller and the memory modules should be sampled.
As contemporary memory systems, in particular dual data rate systems, progress to ever higher clock rates and data transfer rates, the challenges presented in carrying out this write levelling process are growing. The corresponding JEDEC specification (JESD79-3E) defines a basic process for alignment correction between DQS and CLK for up to one clock cycle under ideal conditions. However, this mechanism has now been found not to be practical in contemporary systems (in particular at the above mentioned high data rates) where system jitter and write levelling uncertainty (tWLH, tWLH) are present. Moreover, contemporary memory systems such as DDR3 memory systems adopt a fly-by signal routing for the clock and command (CLK/CMD) signals transmitted from the memory controller to the memory modules, wherein the CLK/CMD signals are routed from one memory module to the next in a concatenated chain. Whilst this improves the signal quality due to an avoidance of the reflection inherent in a branched topology, it also necessarily increases the CLK/CMD path length for memory modules later in the concatenation. In particular some dual in-line memory module (DIMM) topologies operating at data rates greater than 1600 Mb/s will require more than one clock cycle of write levelling and have stringent clock jitter requirements. The DQS path in PHY (i.e. on the memory controller) is typically rather long and the dynamic random access memory (DRAM) clock path is usually matched to the DQS path on chip. However, increasing the length of the DRAM clock path, whilst on the one hand allowing it to provide the required degree of write levelling, on the other hand also makes it more susceptible to power supply noise induced jitter, unless built using current mode logic (CML) which typically has undesirably high power requirements and further requires custom implementation.
Accordingly it would be desirable to provide a method and apparatus for allowing the required write levelling to be carried out whilst further satisfying the contemporary stringent clock jitter requirements.